The present invention relates to a method of manufacturing semiconductor devices, e.g., MOS and CMOS transistors and integrated circuits containing such transistors on a common semiconductor substrate, with improved processing methodology resulting in increased reliability, quality, and device performance. The present invention has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 xcexcm, e.g., about 0.15 xcexcm and below.
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 xcexcm and below, such as 0.15xcexcm and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput and product yield for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor manufacturing techniques.
A conventional approach for forming active devices, such as MOS and/or CMOS transistors in or on a semiconductor substrate, involves formation of a thin gate oxide layer on the active areas of a cleaned surface of the semiconductor substrate, e.g., an about 25-50 xc3x85 thick silicon oxide layer in the case of silicon-based devices, followed by blanket deposition thereon of a gate material comprising a relatively thin layer of polysilicon. Inasmuch as the quality of the gate oxide is critical for good device performance, great care is taken during and between these steps to prevent contamination of the gate oxide. For example, the oxidation step for forming the gate oxide layer is typically performed in dedicated furnace tubes, and a direct transfer from gate oxidation to poly deposition is utilized in order to minimize exposure of unprotected gate oxide. A gate mask is then employed for defining the gate area(s) in resist and the polysilicon layer is etched away from the other areas.
In subsequent ion implantation processing to form lightly- or moderately-doped source/drain extension implants in the semiconductor substrate, the implantation energies are carefully selected to be low enough to prevent penetration of the gate oxide by implanted dopant ions. Similarly, the implantation energies of e.g., arsenic and boron difluoride ions employed during formation of moderately- to heavily-doped source/drain implants are selected as to be low enough to form shallow junction n-channel and p-channel S/D regions in the substrate while doping the polysilicon gate areas to relatively good conductivities with minimal dopant penetration/diffusion into the underlying gate oxide. Dopant depletion the gate polysilicon disadvantageously reduces the conductivity thereof, whereas dopant penetration and contamination of the gate oxide layer adversely results in a reduction of the insulative properties thereof. In addition, such boron penetration of the gate oxide degrades MOS transistor properties such as, for example, threshold voltage VT.
However, such standard precautions as described above are generally insufficient for adequately minimizing or preventing deleterious dopant depletion of the polysilicon gate layer and resultant dopant penetration of the underlying gate oxide layer. This is particularly problematic in the case of boron-containing p-type dopants, principally due to the ease with which boron ions or atoms diffuse in silicon substrates. Boron depletion from p+ gate polysilicon layers with attendant gate oxide penetration is of special concern when subsequent device processing includes post-implantation annealing, e.g., RTA, for dopant activation and lattice damage relaxation. For example, it has been reported that boron will penetrate gate oxides of about 12.6 nm or less thick during a 900xc2x0 C. 30 minute post-implant anneal in nitrogen. Such boron penetration results in a positive shift in the threshold voltage VT of implanted PMOS transistors. In some instances, boron penetration will continue into underlying silicon. It has also been determined that the presence of fluorine in the gate oxide exacerbates the boron penetration problem. Such boron penetration of the gate oxide can readily occur if the PMOS source/drain regions are implanted with BF2 ion species. As a consequence, implantation of elemental boron ions is considered inherently superior to BF2 implantation for surface-channel PMOS devices in CMOS technologies utilizing p-doped polysilicon gates.
Accordingly, there exists a need for improved semiconductor methodology for fabrication of MOS and/or CMOS transistors and integrated circuit devices comprising a plurality of such devices which does not suffer from the above-described drawbacks associated with the conventional methodology. There exists a need for an improved process for fabricating MOS and/or CMOS transistors which minimizes or substantially eliminates deleterious dopant depletion of the gate polysilicon and associated dopant penetration of the gate oxide, and which provides a significant improvement in transistor threshold voltage stability, and device quality and performance.
An advantage of the present invention is an improved method for fabricating semiconductor devices utilizing gate oxide and polysilicon gate layers wherein dopant depletion of the gate polysilicon layers and resultant dopant penetration of underlying gate oxide layers are minimized or substantially eliminated.
Another advantage of the present invention is an improved method for fabricating a MOS or CMOS transistor device comprising eliminating or substantially reducing depletion of boron p-type dopant from a gate polysilicon layer and its attendant penetration of an underlying gate oxide layer.
Still another advantage of the present invention is an improved silicon-based MOS or CMOS transistor device comprising a polysilicon gate having a reduced amount of boron depletion therefrom and an underlying silicon oxide gate insulator layer having reduced boron penetration thereinto.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of fabricating a semiconductor device comprising a thin gate insulating layer and an overlying electrically conductive gate layer, which method comprises the sequential steps of:
(a) providing a first, heavily-doped, p+ or n+ type semiconductor substrate of predetermined thickness and having opposed, spaced-apart, first and second major surfaces with a plurality of side surfaces therebetween;
(b) forming a thin gate insulating layer on the first major surface of the first substrate;
(c) implanting impurities into the exposed surface of the gate insulating layer, the impurities passing through the gate insulating layer and penetrating the underlying first semiconductor substrate for a predetermined depth below the first major surface, the structural integrity of the first substrate being weakened at the predetermined depth;
(d) cleaving the implanted first substrate along a cleavage plane parallel to the first major surface and located at the predetermined depth;
(e) providing a second semiconductor substrate of same conductivity type as the first semiconductor substrate, the second substrate having opposed, spaced-apart first and second major surfaces; and
(f) bonding the exposed surface of the gate insulating insulating layer of the cleaved first substrate to the first major surface of the second substrate; whereby the first, heavily-doped semiconductor substrate forms an electrically conductive gate electrode in contact with the thin gate insulator layer, and wherein dopant depletion of the first semiconductor substrate with attendant penetration of the dopant into the underlying thin gate insulator layer is minimized or substantially prevented.
In embodiments according to the invention, step (a) comprises providing a silicon semiconductor substrate, preferably a polysilicon substrate; step (b) comprises forming a silicon oxide gate insulating layer about 25-50 xc3x85 thick; step (c) comprises ion implantation of the impurities, e.g., H+ or He+ ions, under conditions selected such that the predetermined depth of penetration into the substrate is substantially equal to a desired thickness of the gate electrode; step (d) comprises forming perforations in the side surfaces of the implanted first semiconductor substrate along the periphery of the cleavage plane; step (e) comprises providing a second semiconductor substrate having a different dopant concentration than the first semiconductor substrate, the second substrate preferably comprising lightly-doped pxe2x88x92 or nxe2x88x92 type monocrystalline silicon; and step (f) comprises bonding by application of heat and/or pressure or by electrostatic bonding.
According to another aspect of the present invention, a method of fabricating a silicon-based MOS-type semiconductor device having a heavily-doped polysilicon gate electrode comprises the sequential steps of:
(a) providing a first, heavily-doped polysilicon semiconductor substrate of one conductivity type and having opposed first and second major surfaces spaced apart a predetermined distance by a plurality of side surfaces;
(b) forming a thin gate insulator comprising an about 25-50 xc3x85 thick silicon oxide layer on the first major surface of the first semiconductor substrate;
(c) implanting H+ or He+ impurity ions into the exposed surface of the silicon oxide gate insulator layer, the H+ or He+ ions passing through the silicon oxide layer and penetrating into the underlying first, heavily-doped polysilicon substrate for a predetermined depth below the first major surface substantially equal to a desired gate electrode thickness, the structural integrity of the first, heavily-doped polysilicon substrate being weakened at the predetermined depth;
(d) cleaving the implanted first, heavily-doped polysilicon substrate along a cleavage plane parallel to the first major surface and located at the predetermined depth, the cleaving including forming perforations in the side surfaces of the impurity implanted first, heavily-doped polysilicon substrate along the periphery of the cleavage plane;
(e) providing a second, lightly-doped monocrystalline silicon substrate of same conductivity type as the first, heavily-doped polysilicon substrate, the second substrate having opposed, spaced-apart, first and second major surfaces; and
(f) bonding the exposed surface of the silicon oxide gate insulator layer of the cleaved first, heavily-doped polysilicon substrate to the first major surface of the second, lightly-doped monocrystalline silicon substrate, whereby the first-heavily-doped polysilicon substrate forms an electrically conductive gate electrode in contact with the silicon oxide gate insulator layer, the second, lightly-doped monocrystalline silicon-second substrate is adapted for source/drain formation therein, and dopant depletion of the first, heavily-doped polysilicon substrate with attendant dopant penetration into the underlying silicon oxide gate insulator layer are minimized or substantially prevented.
According to still another aspect of the present invention, improved submicron-dimensioned silicon-based MOS and/or CMOS transistor devices made according to the abovementioned steps (a)-(f) are provided, wherein a heavily boron-doped polysilicon gate electrode incurs reduced or no boron depletion with attendant penetration of the underlying silicon oxide gate insulator layer.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.